1. Field of the Invention
Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode.
2. Description of the Related Art
Semiconductor memory devices may be categorized as volatile semiconductor memory devices (e.g., a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device) or non-volatile semiconductor memory devices (e.g., a read only memory (ROM) device). The volatile semiconductor memory devices may lose data stored therein as a time elapses. The non-volatile semiconductor memory devices, which may have a slower date processing rate, may maintain data stored therein even though a power source may be turned off.
Because non-volatile semiconductor memory devices have unlimited storage capacity, a flash memory device (e.g., an electrically erasable and programmable ROM (EEPROM) device) storing data therein and outputting the data therefrom may be in demand. A memory cell in the flash memory device may generally include a floating gate having a vertically stacked structure formed on a silicon substrate.
FIG. 1 is a diagram illustrating a cross sectional view of a flash memory cell manufactured according to conventional methods.
Referring to FIG. 1, a gate electrode having a stacked structure in a flash memory cell may include a tunnel oxide layer 12 (e.g., a gate oxide layer) formed on a semiconductor substrate 10, a floating gate 14 formed on the tunnel oxide layer 12, a dielectric interlayer 16 (e.g., an oxide/nitride/oxide (ONO) layer) formed on the tunnel oxide layer 12 and/or a control gate 22 formed on the dielectric interlayer 16. Reference numeral 24 represents a hard mask layer pattern, which functions as an etching mask.
The floating gate 14 may function as a tunneling source that affects electrical characteristics of charges in the tunnel oxide layer 12 when data is programmed into or erased from the memory cell.
The dielectric interlayer 16 may reserve, or maintain, charges accumulated in the floating gate 14.
The control gate 22 may include a polysilicon layer 18 and a tungsten silicide layer 20 in order that the control gate 22 achieves a relatively lower resistance. When a voltage is applied to the control gate 22, the control gate 22 may supply electrons to the semiconductor substrate 10. The electrons may migrate from the semiconductor substrate 10 to the floating gate 14 or electrons in the floating gate 14 may migrate to the semiconductor substrate 10.
The flash memory cell, including the stacked gate electrode, may store data by supplying electrons to the floating gate 14 or extracting electrons from the floating gate 14 when an appropriate voltage is applied to the control gate 20 and the semiconductor substrate 10.
An edge profile of the gate electrode may have an effect on electrical characteristics and the reliability of a transistor having the gate electrode. For example, when the gate electrode has an edge portion having a sharper profile caused by damage from an etching process, an intensive electric field may occur around the edge portion increasing the likelihood of a leakage current. The memory cell may have deteriorated electrical characteristics and degraded reliability thereof.
A re-oxidation process has been acknowledged in order to repair damage to a sidewall of the gate electrode and a surface of the semiconductor substrate. The damage may occur in an etching process for forming the gate electrode. The re-oxidation process may round off a lower edge portion of the gate electrode.
In the re-oxidation process, a surface of the semiconductor substrate 10, the sidewall of the floating gate 14 and the side wall of the control gate 22 may be oxidized by reacting silicon atoms with oxidants to form an oxide layer 26 on the surface of the semiconductor substrate 10, the sidewall of the floating gate 14 and the sidewall of the control gate 22.
The oxidants may penetrate into a lateral portion of the tunnel oxide layer 12 such that bird's beak phenomenon occurs at the lateral portion of the tunnel oxide layer 12. Bird's beak phenomenon results from a two-dimensional oxidation that may occur at an edge of a field oxide during the re-oxidation process. As such, oxidation extends into an active area at a surface underneath a silicon nitride forming a bird's beak. Because of the bird's beak, an effective area of the active region may be reduced. In the bird's beak region of the tunnel oxide layer 12, oxide thinning may occur. The tunnel oxide layer 12 may expand at the end portions thereof due to the bird's beak phenomenon.
When the tunnel oxide layer 12 expands at the lateral portion, the tunnel oxide layer 12 may have an increased overall thickness due to the gate electrode having a reduced width. It may be necessary to prevent, or retard, an increase in the overall thickness of the tunnel oxide layer caused by the bird's beak phenomenon.
When the re-oxidation process includes a thermal oxidation process (e.g., a dry oxidation process or a wet oxidation process), it may be difficult to prevent or retard an increase in the overall thickness of the tunnel oxide layer by controlling the bird's beak phenomenon. A radical re-oxidation process using radicals having a desired reactivity with the silicon atoms and the oxidants has been suggested.
According to the radical re-oxidation process, a hydrogen gas and an oxygen gas may be activated such that radicals of the hydrogen gas and the oxygen gas are produced. The radicals may react with the silicon atoms. In the radical re-oxidation process, an oxidation reaction may actively occur. An oxide layer having a uniform thickness may be formed irrespective of a profile of an oxidation reaction site. Dangling bonds in the oxide layer may be reduced such that the oxide layer may have an increased density thereof. Also, damage in the oxide layer may decrease, forming an oxide layer having desired mechanical characteristics.
FIG. 2 is a graph showing thermomechanical reaction stability of partial pressures of an oxygen gas relative to temperatures of a silicon substrate according to conventional methods.
Referring to FIG. 2, as a temperature of a silicon substrate increases, a partial pressure of an oxygen gas (e.g., a concentration of the oxygen gas), necessary for an oxidation process, may increase. When the temperature of the silicon substrate increases under a constant partial pressure of the oxygen gas, the concentration of the oxygen gas may be substantially lower than a desired concentration of the oxygen gas, which is needed to perform the oxidation process. As illustrated in FIG. 1, a reduction reaction, which vaporizes silicon of the silicon substrate into silicon oxide (in a vapor phase), may occur when the semiconductor substrate includes a silicon substrate. A surface of the silicon substrate may be slightly etched as a result of the reduction reaction. The etched silicon substrate may cause pitting at a lower edge portion of the floating gate 14. When pitting occurs around the silicon substrate, a haze may form over the silicon substrate.
In the radical re-oxidation process, the metal silicide layer pattern 20 may expand at a sidewall thereof to generate a hump at the sidewall of the metal silicide layer pattern 20. A bridge may form between adjacent gate electrodes in the memory cell.